Field
The disclosed technology relates generally to the field of semiconductor devices and specifically to three-dimensional non-volatile memories, such as vertical NAND strings and to methods of making such devices.
Description of the Related Technology
Vertical channel, Bit Cost Scalable (BiCS) NAND memory and U-shaped (i.e. “pipe-shaped”) BiCS (p-BiCS) were developed for ultra-high density storage devices. However, earlier BiCS and p-BiCS 3D NAND architectures suffer from relatively high control gate/word line resistances and capacitances. These resistances and capacitances reduce cell efficiency and increase the power consumption of the memory device.
When thus stacking many cells on a memory chip in such a NAND configuration, a complication arises how to connect the cells at the bottom of the stack. In practice such bottom connection cannot be done by a diffused region, as is done for example in NOR Flash, because such connection would cause very large series resistance. This resistance would compromise the read-out speed of the memory, having a very small read current already. Alternatively, for example, metal plugs may be used to connect the cells to the bottom, like in the Samsung V-NAND configuration as disclosed e.g. in US2010/0155810 (FIG. 1). Metal plugs could be used since this replacement gate technology requires large slits about every four cells in use. However, such manufacturing process requires very careful processing involving high aspect ratio etch and deposition thereby risking short-circuiting between the cell planes etc. As such, this approach is complicated and costly in terms of area consumption.
Another option may be to provide a pipeline in the memory chip, which connects adjacent strings at their bottom thereby creating a series connection between them. In this approach all contacts can be made at the upper side of the series connected strings as disclosed in e.g. US2014/0361360 (FIG. 2) forming a so-called horizontal pipeline. However, constructing such a horizontal pipeline in the memory array is very complicated. Layers formed have to be conformal along this ‘tunnel’ as well. Moreover, since the cells on the parallel sides of the pipeline belong to the same cell string, they can no longer share the same word line controlling the operation of a cell at a particular position or height in the string. As a consequence, a slit is needed between both parts of the string. Theoretically a slit would be needed every two cells, which is strongly compromises memory density.
Accordingly, there is a need for novel and improved three-dimensional non-volatile memory devices and fabrication methods thereof. Embodiments of the disclosed technology provide modification or alternatives for the BiCS and p-BiCS processes and allow high density NAND architectures with easier process control.